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DATA SHEET
MOS INTEGRATED CIRCUIT
PD784035(A), 784036(A)
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The PD784036(A) is a product of the PD784038 sub-series in the 78K/IV series. A stricter quality assurance program applies to the PD784036(A) than the PD784036 (standard product). In terms of the NEC quality, the
PD784036(A) is classified as the special grade.
The PD784036(A) contains various peripheral hardware such as ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance CPU. In addition, the PD78P4038(A) (one-time PROM or EPROM product), which can be operated within the same power supply voltage ranges as masked-ROM products, and development tools are supported. For specific functions and other detailed information, consult the following user's manual. This manual is required reading for design work. PD784038, 784038Y Sub-Series User's Manual, Hardware : U11316E 78K/IV Series User's Manual, Instruction : U10905E
FEATURES
* Higher reliability than the PD784036 (Refer to Quality Grade on NEC Semiconductor Devices (Document number C11531E).) * Minimum instruction execution time: 125 ns (at 32 MHz) * Number of I/O ports: 64 * Timer/counters 16-bit timer/counter x 3 units 16-bit timer x 1 unit * A/D converter: 8-bit resolution x 8 channels * D/A converter: 8-bit resolution x 2 channels * Standby function HALT/STOP/IDLE mode * PWM outputs: 2 * Serial interface: 3 channels UART/IOE (3-wire serial I/O): 2 channels CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel * Clock frequency division function * Watchdog timer: 1 channel * Clock output function Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 * Power supply voltage: VDD = 2.7 to 5.5 V
APPLICATIONS
Controllers for automobile electronic control systems, gas detector circuit-breakers, various types of safety equipment, etc.
This manual describes the PD784036(A) unless otherwise specified.
The information in this document is subject to change without notice.
Document No. U13010EJ1V0DS00 (1st edition) Date Published December 1997 J Printed in Japan
(c)
1997
PD784035(A), 784036(A)
ORDERING INFORMATION
Part number Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic QFP (14 x 14 mm) Internal ROM (bytes) 48K 64K Internal RAM (bytes) 2 048 2 048
PD784035GC(A)-xxx-3B9 PD784036GC(A)-xxx-3B9
Remark xxx is a ROM code suffix.
QUALITY GRADE
Part number Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic QFP (14 x 14 mm) Quality grade Special Special
PD784035GC(A)-xxx-3B9 PD784036GC(A)-xxx-3B9
Remark xxx is a ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
PD784035(A), 784036(A)
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
: Under mass production : Under development
I2C bus supported
Multimaster I2C bus supported
PD784038Y
Standard models
PD784225Y PD784225
80 pins, added ROM correction Multimaster I2C bus supported
PD784038
Enhanced internal memory capacity, pin compatible with the PD784026 Multimaster I2C bus supported
PD784026
Enhanced A/D, 16-bit timer, and power management
PD784216Y PD784216
100 pins, enhanced I/O and internal memory capacity
PD784218Y PD784218
Enhanced internal memory capacity, added ROM correction
PD784054 PD784046
ASSP models Equipped with 10-bit A/D
PD784955
For DC inverter control
PD784908
Equipped with IEBusTM controller
PD784943
For CD-ROM
Multimaster I2C bus supported
PD784928Y PD784928
Enhanced function of the PD784915
PD784915
For software servo control, equipped with analog circuit for VCR, enhanced timer
3
PD784035(A), 784036(A)
FUNCTIONS
Product Item Number of basic instructions (mnemonics) General-purpose register Minimum instruction execution time Internal memory Memory space I/O ports Total Input Input/output Additional function pinsNote ROM RAM 113 8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping) 125 ns/250 ns/500 ns/1 000 ns (at 32 MHz) 48K bytes 2 048 bytes Program and data: 1M byte 64 8 56 64K bytes
PD784035(A)
PD784036(A)
Pins with pull- 54 up resistor LED direct drive outputs Transistor direct drive 24 8 4 bits x 2, or 8 bits x 1 Timer/counter 0: (16 bits) Timer register x 1 Capture register x 1 Compare register x 2 Timer register x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer register x 1 Capture register x 1 Capture/compare register x 1 Compare register x 1 Timer register x 1 Compare register x 1 Pulse output capability * Toggle output * PWM/PPG output * One-shot pulse output Pulse output capability * Real-time output (4 bits x 2)
Real-time output ports Timer/counter
Timer/counter 1: (8/16 bits)
Timer/counter 2: (8/16 bits)
Pulse output capability * Toggle output * PWM/PPG output
Timer 3 (8/16 bits) PWM outputs Serial interface A/D converter D/A converter Clock output Watchdog timer Standby Interrupt Hardware source Software source Nonmaskable Maskable
:
12-bit resolution x 2 channels UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator) CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel 8-bit resolution x 8 channels 8-bit resolution x 2 channels Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16 (can be used as a 1-bit output port) 1 channel HALT/STOP/IDLE mode 23 (16 internal, 7 external (sampling clock variable input: 1)) BRK instruction, BRKCS instruction, operand error 1 internal, 1 external 15 internal, 6 external * 4-level programmable priority * 3 operation statuses: vectored interrupt, macro service, context switching
Supply voltage Package
VDD = 2.7 to 5.5 V 80-pin plastic QFP (14 x 14 mm)
Note Additional function pins are included in the I/O pins.
4
PD784035(A), 784036(A)
CONTENTS
1. 2. 3. 4. 5.
DIFFERENCES BETWEEN PD784038 SUB-SERIES SPECIAL PRODUCTS .................... DIFFERENCES BETWEEN STANDARD AND SPECIAL PRODUCTS .................................. PIN CONFIGURATION (TOP VIEW) ......................................................................................... BLOCK DIAGRAM ..................................................................................................................... LIST OF PIN FUNCTIONS .........................................................................................................
5.1 5.2 5.3 Port Pins ............................................................................................................................................ Non-Port Pins ................................................................................................................................... I/O Circuits for Pins and Handling of Unused Pins ....................................................................
7 7 8 10 11
11 13 15
6.
CPU ARCHITECTURE ...............................................................................................................
6.1 6.2 Memory Space .................................................................................................................................. CPU Registers .................................................................................................................................. 6.2.1 6.2.2 6.2.3 General-purpose registers ................................................................................................ Control registers ................................................................................................................ Special function registers (SFRs) ....................................................................................
18
18 21 21 22 23
7.
PERIPHERAL HARDWARE FUNCTIONS ................................................................................
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Ports ................................................................................................................................................... Clock Generator ............................................................................................................................... Real-Time Output Port ..................................................................................................................... Timers/Counters ............................................................................................................................... PWM Output (PWM0, PWM1) .......................................................................................................... A/D Converter ................................................................................................................................... D/A Converter ................................................................................................................................... Serial Interface ................................................................................................................................. 7.8.1 7.8.2 7.9 Asynchronous serial interface/three-wire serial I/O (UART/IOE) ................................ Synchronous serial interface (CSI) ..................................................................................
28
28 29 31 32 34 35 36 37 38 40 41 42 42
Clock Output Function ....................................................................................................................
7.10 Edge Detection Function ................................................................................................................ 7.11 Watchdog Timer ...............................................................................................................................
8.
INTERRUPT FUNCTION ............................................................................................................
8.1 8.2 8.3 8.4 8.5 Interrupt Source ............................................................................................................................... Vectored Interrupt ............................................................................................................................ Context Switching ............................................................................................................................ Macro Service ................................................................................................................................... Examples of Macro Service Applications .....................................................................................
43
43 45 46 46 47
5
PD784035(A), 784036(A)
9. LOCAL BUS INTERFACE .........................................................................................................
9.1 9.2 9.3 9.4 9.5 Memory Expansion .......................................................................................................................... Memory Space .................................................................................................................................. Programmable Wait ......................................................................................................................... Pseudo-Static RAM Refresh Function .......................................................................................... Bus Hold Function ...........................................................................................................................
49
49 50 51 51 51
10. STANDBY FUNCTION ............................................................................................................... 11. RESET FUNCTION ..................................................................................................................... 12. INSTRUCTION SET .................................................................................................................... 13. ELECTRICAL CHARACTERISTICS ......................................................................................... 14. PACKAGE DRAWINGS ............................................................................................................. 15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A DEVELOPMENT TOOLS .......................................................................................... APPENDIX B RELATED DOCUMENTS .........................................................................................
52 53 54 59 80 81 82 85
6
PD784035(A), 784036(A)
1. DIFFERENCES BETWEEN PD784038 SUB-SERIES SPECIAL PRODUCTS
The only difference between the PD784031(A), PD784035(A), and PD784036(A) is their capacity of internal memory. The PD78P4038(A) is produced by replacing the masked ROM in the PD784031(A), PD784035(A), or
PD784036(A) with 128K-byte one-time PROM or EPROM. Table 1-1 shows the differences between these products.
Table 1-1. Differences between the PD784038 Sub-Series Special Products
Product Item Internal ROM None 48K bytes (masked ROM) 64K bytes (masked ROM)
PD784031(A)
PD784035(A)
PD784036(A)
PD78P4038(A) (under develoment)
128K bytes (one-time PROM or EPROM) 4 352 bytes
Internal RAM
2 048 bytes
2. DIFFERENCES BETWEEN STANDARD AND SPECIAL PRODUCTS
Table 2-1 shows the differences between standard and special products. Table 2-1. Differences between Standard and Special Products
Product Item Quality grade Package Special 80-pin plastic QFP (14 x 14 x 2.7 mm)
PD784035(A), PD784036(A)
PD784035, PD784036, PD784037, PD784038
Standard 80-pin plastic QFP (14 x 14 x 2.7 mm) 80-pin plastic QFP (14 x 14 x 1.4 mm) 80-pin plastic TQFP (fine pitch, 12 x 12 mm)
7
PD784035(A), 784036(A)
3. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 x 14 mm)
PD784031GC(A)-xxx-3B9, PD784036GC(A)-xxx-3B9
P25/INTP4/ASCK/SCK1
P31/ TxD/SO1
P23/INTP2/CI
P30/RxD/SI1
P22/INTP1
P24/INTP3
P26/INTP5
P21/INTP0
P77/ANI7
P76/ANI6
P32/SCK0/SCL P33/SO0/SDA P34/ TO0 P35/ TO1 P36/ TO2 P37/ TO3 RESET VDD1 X2 X1 VSS1 P00 P01 P02 P03 P04 P05 P06 P07 P67/REFRQ/HLDAK
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P75/ANI5
P20/NMI
P27/SI0
AVREF3
AVREF2
AVREF1
ANO1
ANO0
AVDD
AVSS
P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 VDD0 P17 P16 P15 P14/TXD2/SO2 P13/RXD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 TESTNote VSS0 ASTB/CLKOUT P40/AD0 P41/AD1 P42/AD2
P66/ WAIT/HLDRQ
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Note
Connect the TEST pin to VSS0 directly.
8
P43/AD3
P65/WR
P64/RD
PD784035(A), 784036(A)
A8-A19 AD0-AD7 ANI0-ANI7 ANO0, ANO1 ASCK, ASCK2 ASTB AVDD AVREF1-AVREF3 AVSS CI CLKOUT HLDAK HLDRQ INTP0-INTP5 NMI P00-P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 : Address bus : Address/data bus : Analog input : Analog output : Asynchronous serial clock : Address strobe : Analog power supply : Reference voltage : Analog ground : Clock input : Clock output : Hold acknowledge : Hold request : Interrupt from peripherals : Non-maskable interrupt : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 P60-P67 P70-P77 RD REFRQ RESET RxD, RxD2 SCK0-SCK2 SCL SDA SI0-SI2 SO0-SO2 TEST TO0-TO3 TxD, TxD2 VDD0, VDD1 VSS0, VSS1 WAIT WR X1, X2 : Port 6 : Port 7 : Read strobe : Refresh request : Reset : Receive data : Serial clock : Serial clock : Serial data : Serial input : Serial output : Test : Timer output : Transmit data : Power supply : Ground : Wait : Write strobe : Crystal
PWM0, PWM1 : Pulse width modulation output
9
PD784035(A), 784036(A)
4. BLOCK DIAGRAM
UART/IOE2 NMI INTP0-INTP5 Programmable interrupt controller Baud-rate generator UART/IOE1 INTP3 TO0 TO1 Timer/counter 0 (16 bits) Baud-rate generator
RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2
SCK0/SCL INTP0 Timer/counter 1 (16 bits) 78K /IV CPU core ROM Clocked serial interface SO0/SDA SI0 Clock output ASTB/CLKOUT AD0-AD7 A8-A15 Bus interface Timer 3 (16 bits) A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK P00-P07
INTP1 INTP2/CI TO2 TO3
Timer/counter 2 (16 bits)
P00-P03 Real-time output port P04-P07 PWM0 PWM PWM1 ANO0 ANO1 AVREF2 AVREF3 RAM
Port 0
Port 1
P10-P17
Port 2 Port 3
P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 RESET TEST X1 X2 VDD0, VDD1 VSS0, VSS1
D/A converter
Port 4 Port 5
ANI0-ANI7 AVDD AVREF1 AVSS INTP5 Watchdog timer A/D converter
Port 6 Port 7
System control
Remark The internal ROM capacity differs for each product.
10
PD784035(A), 784036(A)
5. LIST OF PIN FUNCTIONS
5.1 Port Pins (1/2)
Pin P00-P07 I/O I/O Dual-function Port 0 (P0): * 8-bit I/O port. * Functions as a real-time output port (4 bits x 2). * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in input mode together. * Can drive a transistor. P10 P11 P12 P13 P14 P15-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34-P37 P40-P47 I/O I/O Input NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0 RxD/SI1 TxD/SO1 SCK0/SCL SO0/SDA TO0-TO3 AD0-AD7 I/O PWM0 PWM1 ASCK2/SCK2 RxD2/SI2 TxD2/SO2 Port 1 (P1): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in input mode together. * Can drive LED. Port 2 (P2): * 8-bit input-only port. * P20 does not function as a general-purpose port (nonmaskable interrupt). However, the input level can be checked by an interrupt service routine. * The use of the pull-up resistors can be specified by software for pins P22 to P27 (in units of 6 bits). * The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by CSIM1. Port 3 (P3): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in input mode together. Port 4 (P4): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together. * Can drive LED. P50-P57 I/O A8-A15 Port 5 (P5): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together. * Can drive LED. Function
11
PD784035(A), 784036(A)
5.1 Port Pins (2/2)
Pin P60-P63 P64 P65 P66 P67 P70-P77
I/O I/O
Dual-function A16-A19 RD WR WAIT/HLDRQ REFRQ/HLDAK Port 6 (P6): * 8-bit I/O port.
Function
* Inputs and outputs can be specified bit by bit. * The use of the pull-up resistors can be specified by software for the pins in the input mode together. Port 7 (P7): * 8-bit I/O port. * Inputs and outputs can be specified bit by bit.
I/O
ANI0-ANI7
12
PD784035(A), 784036(A)
5.2 Non-Port Pins (1/2)
Pin TO0-TO3 CI RXD RXD2 TXD TXD2 ASCK ASCK2 SDA SI0 SI1 SI2 SO0 SO1 SO2 SCK0 SCK1 SCK2 SCL NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 RD WR WAIT REFRQ HLDRQ HLDAK ASTB CLKOUT I/O Output Output Output Output Input Output Input Output Output Output Input I/O Output I/O Input Input Output I/O Output Input Input Dual-function P34-P37 P23/INTP2 P30/SI1 P13/SI2 P31/SO1 P14/SO2 P25/INTP4/SCK1 P12/SCK2 P33/SO0 P27 P30/RXD P13/RXD2 P33/SDA P31/TXD P14/TXD2 P32/SCL P25/INTP4/ASCK P12/ASCK2 P32/SCK0 P20 P21 P22 P23/CI P24 P25/ASCK/SCK1 P26 P40-P47 P50-P57 P60-P63 P64 P65 P66/HLDRQ P67/HLDAK P66/WAIT P67/REFRQ CLKOUT ASTB Timer output Input of a count clock for timer/counter 2 Serial data input (UART0) Serial data input (UART2) Serial data output (UART0) Serial data output (UART2) Baud rate clock input (UART0) Baud rate clock input (UART2) Serial data I/O (2-wire serial I/O) Serial data input (3-wire serial I/O0) Serial data input (3-wire serial I/O1) Serial data input (3-wire serial I/O2) Serial data output (3-wire serial I/O0) Serial data output (3-wire serial I/O1) Serial data output (3-wire serial I/O2) Serial clock I/O (3-wire serial I/O0) Serial clock I/O (3-wire serial I/O1) Serial clock I/O (3-wire serial I/O2) Serial clock I/O (2-wire serial I/O) External interrupt reguest * Input of a count clock for timer/counter 1 * Capture/trigger signal for CR11 or CR12 * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR22 * Input of a count clock for timer/counter 2 * Capture/trigger signal for CR21 * Input of a count clock for timer/counter 0 * Capture/trigger signal for CR02 Input of a conversion start trigger for A/D converter Time multiplexing address/data bus (for connecting external memory) High-order address bus (for connecting external memory) High-order address bus during address expansion (for connecting external memory) Strobe signal output for reading the contents of external memory Strobe signal output for writing on external memory Wait signal insertion Refresh pulse output to external pseudo static memory Input of bus hold request Output of bus hold response Latch timing output of time multiplexing address (A0-A7) (for connecting external memory) Clock output Function
13
PD784035(A), 784036(A)
5.2 Non-Port Pins (2/2)
Pin RESET X1 X2 ANI0-ANI7 ANO0, ANO1 AVREF1 AVREF2, AVREF3 AVDD AVSS VDD0Note 1 VDD1Note 1 VSS0Note 2 VSS1Note 2 TEST I/O Input Input Input Output P70-P77 Dual-function Chip reset Crystal input for system clock oscillation (A clock pulse can also be input to the X1 pin.) Analog voltage inputs for the A/D converter Analog voltage outputs for the D/A converter Application of A/D converter reference voltage Application of D/A converter reference voltage Positive power supply for the A/D converter Ground for the A/D converter Positive power supply of the port part Positive power supply except for the port part Ground of the port part Ground except for the port part Directly connect to VSS0. (The TEST pin is for the IC test.) Function
Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin. 2. The potential of the VSS0 pin must be equal to that of the VSS1 pin.
14
PD784035(A), 784036(A)
5.3 I/O Circuits for Pins and Handling of Unused Pins
Table 5-1 describes the types of I/O circuits for pins and the handling of unused pins. See Figure 5-1 for the configuration of these various types of I/O circuits. Table 5-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)
Pin P00-P07 P10/PWM0 P11/PWM1 P12/ASCK2/SCK2 P13/RxD2/SI2 P14/TxD2/SO2 P15-P17 P20/NMI P21/INTP0 P22/INTP1 P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1
I/O circuit type 5-H
I/O I/O
Recommended connection method for unused pins Input state : Connect these pins to VDD0. Output state: Leave open.
8-C 5-H
2
Input
Connect these pins to VDD0 or VSS0.
2-C
Connect these pins to VDD0.
8-C
I/O
Input state : Connect these pins to VDD0. Output state: Leave open.
P26/INTP5 P27/SI0 P30/RxD/SI1 P31/TxD/SO1 P32/SCK0/SCL P33/SO0/SDA P34/TO0-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7
2-C
Input
Connect these pins to VDD0.
5-H
I/O
Input state : Connect these pins to VDD0. Output state: Leave open.
10-B
5-H
20-A
I/O
Input state : Connect these pins to VDD0 or VSS0. Output state: Leave open.
ANO0, ANO1 ASTB/CLKOUT
12 4-B
Output
Leave open.
15
PD784035(A), 784036(A)
Table 5-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)
Pin RESET TEST AVREF1-AVREF3 AVSS AVDD
I/O circuit type 2 1-A -
I/O Input
Recommended connection method for unused pins Connect this pin to VSS0 directly. Connect these pins to VSS0.
Connect this pin to VDD0.
Caution When I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD0 through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software). Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product. (Some circuits are not included.)
16
PD784035(A), 784036(A)
Figure 5-1. I/O Circuits for Pins
Type 1-A
VDD0 P IN
Type 2-C
VDD0
P
Pull-up enable
N VSS0
Type 2
Schmitt trigger input with hysteresis characteristics IN
IN Type 5-H Schmitt trigger input with hysteresis characteristics Type 4-B
VDD0 Pull-up enable Data
VDD0 Data
P VDD0 P IN/OUT
P OUT
Output disable
N VSS0
Output disable Input enable
N VSS0
Push-pull output which can output high impedance (both the positive and negative channels are off.)
Type 8-C
VDD0 Pull-up enable Data
Type 12
P VDD0 P IN/OUT
Analog output voltage
P OUT N
Output disable
N VSS0
Type 10-B VDD0
Type 20-A
Data
VDD0 P IN/OUT
Pull-up enable VDD0 Data Open drain Output disable P
P
Output disable N VSS0
IN/OUT N VSS0
Comparator + - AVREF AVSS (Threshold voltage) Input enable P N
17
PD784035(A), 784036(A)
6. CPU ARCHITECTURE
6.1 Memory Space
A 1M-byte memory space can be accessed. By using a LOCATION instruction, mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed after a reset, and can be used only once. (1) When the LOCATION 0 instruction is executed * Internal memory The table below indicates the internal data areas and internal ROM areas of each product.
Product name Internal data area 0F700H-0FFFFH Internal ROM area 00000H-0BFFFH 00000H-0F6FFH
PD784035(A) PD784036(A)
Caution The following internal ROM areas, existing at the same addresses as the internal data areas, cannot be used when the LOCATION 0 instruction is executed:
Product name
Unusable area 0F700H-0FFFFH (2 304 bytes)
PD784035(A) PD784036(A)
* External memory External memory is accessed in external memory expansion mode. (2) When the LOCATION 0FH instruction is executed * Internal memory The table below lists the internal data areas and internal ROM areas for each product.
Product name Internal data area FF700H-FFFFFH Internal ROM area 00000H-0BFFFH 00000H-0FFFFH
PD784035(A) PD784036(A)
* External memory External memory is accessed in external memory expansion mode.
18
Figure 6-1. PD784035(A) Memory Map
When the LOCATION 0 instruction is executed FF F FF H
FFF FFF FFF FFF
When the LOCATION 0FH instruction is executed
F F H Special function registers (SFRs) DFH D 0 H Note 1 (256 bytes) 0 0H
0 FE FFH External memory (960K bytes)Note 1 General-purpose registers (128 bytes) 0 FE 8 0H 0 FE 7FH 0 FE 2FH Macro service control 0 FE 0 6H word area (42 bytes) Data area (512 bytes) 0 FD 0 0H 0 FC FFH 0 F 7 0 0H 0B F FFH External memory (14 080 bytes)Note 1 Program/data area (48K bytes)
Note 2
FFE FFH
FFE FFH Internal RAM (2 048 bytes)
FFE 8 0H FFE 7FH FFE 2FH FFE 0 6H FFD 0 0H FFC FFH FF7 0 0H
FF7 0 0H FF6 FFH
10 0 00H 0 F F FF H 0 F F DF H 0 F F D0 H 0FF 0 0H 0 F E FF H
Special function registers (SFRs)
Note 1
(256 bytes)
Internal RAM (2 048 bytes) 0F 7 0 0H 0 F 6 FF H
Program/data area (1 536 bytes)
External memory (997 120 bytes)Note 1
PD784035(A), 784036(A)
0 1 0 0 0H 0 0 F FFH 0 0 8 0 0H 0 0 7 FFH CALLF entry area (2K bytes)
1 00 0 0H 0FF FFH 0C0 0 0H 0BF FFH
Note 2
0C 0 0 0 H 0B F FF H Internal ROM (48K bytes)
0 0 0 8 0H 0 0 0 7FH CALLT table area 0 0 0 4 0H (64 bytes) 0 0 0 3FH Vector table area 0 0 0 0 0H (64 bytes) 0 00 0 0H
Internal ROM (48K bytes)
00 0 00H
Notes 1. Accessed in external memory expansion mode.
19
2. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
20
When the LOCATION 0 instruction is executed F FFF FH External memory (960K bytes)Note 1 1 000 0H 0 FFF FH 0 FFDFH 0 FFD0 H 0 FF 0 0 H 0 FEF FH
Special function registers (SFRs)
Note 1
Figure 6-2. PD784036(A) Memory Map
When the LOCATION 0FH instruction is executed
F F F F F F F F FFF FDF FD0 F00 H H H H Special function registers (SFRs)
Note 1
(256 bytes)
0 FEF FH General-purpose registers (128 bytes) 0 FE8 0 H 0 FE7 FH 0 FE2 FH Macro service control 0 FE0 6 H word area (42 bytes) Data area (512 bytes) Internal RAM (2 048 bytes) 0 F70 0H 0 F 6 F FH 0 FD0 0 H 0 FCF FH 0 F70 0H Program/data area (1 536 bytes)
F FEF FH
F FEF FH Internal RAM (2 048 bytes)
F FE8 0 H F FE7 FH F FE2 FH F FE0 6 H F FD0 0 H F FCF FH F F70 0H 0 FFF FH
F F70 0H F F 6 F FH
(256 bytes)
External memory (980 736 bytes)Note 1
Note 2
0 F 6 F FH Program/data areaNote 3 0 100 0H 0 0 FF FH Internal ROM (63 232 bytes)
Note 4
CALLF entry area (2K bytes) 0 080 0H 0 0 7 F FH 0 008 0H 0 0 0 7 FH CALLT table area 0 0 0 4 0 H (64 bytes) 0 0 0 3 FH Vector table area
1 000 0H 0 FFF FH
PD784035(A), 784036(A)
Internal ROM (64K bytes) 0 000 0H
Note 4
0 000 0H
0 0 0 0 0 H (64 bytes)
Notes 1. Accessed in external memory expansion mode. 2. This 2304-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed. 3. When the LOCATION 0 instruction is executed : 63 232 bytes When the LOCATION 0FH instruction is executed: 65 536 bytes 4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
PD784035(A), 784036(A)
6.2 6.2.1 CPU Registers General-purpose registers
A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers. Eight banks of this register set are provided. The user can switch between banks by software or the context switching function. General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto internal RAM. Figure 6-3. General-Purpose Register Format
A (R1) AX (RP0) B (R3) BC (RP1) R5 RP2 R7 RP3 V VVP (RG4) U T W R9 VP (RP4)
X (R0) C (R2) R4 R6 R8
R11 R10 UUP (RG5) UP (RP5) D (R13) E (R12) TDE (RG6) DE (RP6) H (R15) L (R14) WHL (RG7) HL (RP7) The character strings enclosed in parentheses represent absolute names. 8 banks
Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers, respectively. However, this function must be used only when using programs for the 78K/III series.
21
PD784035(A), 784036(A)
6.2.2 Control registers
(1) Program counter (PC) This register is a 20-bit program counter. The program counter is automatically updated by program execution. Figure 6-4. Format of Program Counter (PC)
19 PC 0
(2) Program status word (PSW) This register holds the CPU state. The program status word is automatically updated by program execution. Figure 6-5. Format of Program Status Word (PSW)
15 PSWH PSW 7 PSWL S 6 Z 5 RSSNote 4 AC 3 IE 2 P/V 1 0 0 CY UF 14 RBS2 13 RBS1 12 RBS0 11 10 9 8
Note This flag is used to maintain compatibility with the 78K/III series. This flag must be set to 0 when programs for the 78K/III series are being used. (3) Stack pointer (SP) This register is a 24-bit pointer for holding the start address of the stack. The high-order 4 bits must be set to 0. Figure 6-6. Format of Stack Pointer (SP)
23 SP 0 0 0
20 0
0
22
PD784035(A), 784036(A)
6.2.3 Special function registers (SFRs)
The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H and 0FFFFHNote. Note Applicable when the LOCATION 0 instruction is executed. FFF00H-FFFFFH when the LOCATION 0FH instruction is executed. Caution Never attempt to access addresses in this area where no SFR is allocated. Otherwise, the
PD784036(A) may be placed in the deadlock state. The deadlock state can be cleared only by
a reset. Table 6-1 lists the special function registers (SFRs). The titles of the table columns are explained below. * Abbreviation ................... Symbol used to represent a built-in SFR. The abbreviations listed in the table are reserved words for the NEC assembler (RA78K4). The C compiler (CC78K4) allows the abbreviations to be used as sfr variables with the #pragma sfr command. * R/W ................................. Indicates whether each SFR allows read and/or write operations. R/W : Allows both read and write operations. R W : Allows read operations only. : Allows write operations only.
* Manipulatable bits .......... Indicates the maximum number of bits that can be manipulated whenever an SFR is manipulated. An SFR that supports 16-bit manipulation can be described in the sfrp operand. For address specification, an even-numbered address must be specified. An SFR that supports 1-bit manipulation can be described in a bit manipulation instruction. * When reset ..................... Indicates the state of each register when RESET is applied.
23
PD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (1/4)
Manipulatable bits AddressNote 0FF00H 0FF01H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF0EH 0FF0FH 0FF10H 0FF12H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF20H 0FF21H 0FF23H 0FF24H 0FF25H 0FF26H 0FF27H 0FF2EH 0FF30H 0FF31H 0FF32H 0FF33H Port 0 buffer register H Compare register (timer/counter 0) Capture/compare register (timer/counter 0) Compare register L (timer/counter 1) Compare register H (timer/counter 1) Capture/compare register L (timer/counter 1) Capture/compare register H (timer/counter 1) Compare register L (timer/counter 2) Compare register H (timer/counter 2) Capture/compare register L (timer/counter 2) Capture/compare register H (timer/counter 2) Compare register L (timer 3) Compare register H (timer 3) Port 0 mode register Port 1 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 7 mode register Real-time output port control register Capture/compare control register 0 Timer output control register Capture/compare control register 1 Capture/compare control register 2 Special function register (SFR) name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Abbreviation P0 P1 P2 P3 P4 P5 P6 P7 Port 0 buffer register L P0L P0H CR00 CR01 CR10 CR10W CR11 CR11W CR20 CR20W CR21 CR21W CR30 CR30W PM0 PM1 PM3 PM4 PM5 PM6 PM7 RTPC CRC0 TOC CRC1 CRC2 10H 00H 10H 00H FFH R R/W R/W 1 bit R/W 8 bits 16 bits 00H Undefined Undefined When reset
Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address.
24
PD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (2/4)
Manipulatable bits AddressNote 1 0FF36H 0FF38H 0FF39H 0FF3AH 0FF3BH 0FF41H 0FF43H 0FF4EH 0FF50H 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF60H 0FF61H 0FF62H 0FF68H 0FF6AH 0FF70H 0FF71H 0FF72H 0FF74H 0FF7DH 0FF80H 0FF81H 0FF82H Prescaler mode register 0 Timer control register 0 Prescaler mode register 1 Timer control register 1 D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register A/D converter mode register A/D conversion result register PWM control register PWM prescaler register PWM modulo register 0 PWM modulo register 1 One-shot pulse output control register I2C bus control register Prescaler mode register for serial clock Synchronous serial interface mode register Timer register 3 Timer register 2 Timer register 1 TM1 TM2 TM3 PRM0 TMC0 PRM1 TMC1 DACS0 DACS1 DAM ADM ADCR PWMC PWPR PWM0 PWM1 OSPC IICC SPRM CSIM R R/W 04H 00H 00H R/W TM3W TM2W TM1W Special function register (SFR) name Capture register (timer/counter 0) Capture register L (timer/counter 1) Capture register H (timer/counter 1) Capture register L (timer/counter 2) Capture register H (timer/counter 2) Port 1 mode control register Port 3 mode control register Register for optional pull-up resistor Timer register 0 Abbreviation CR02 CR12 CR12W CR22 CR22W PMC1 PMC3 PUO TM0 RNote 2 03H 00H Undefined 05H 00H Undefined 11H 00H 11H 00H R/W R/W 1 bit R 0000H 00H 8 bits 16 bits 0000H When reset
Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 2. Some registers cannot read. Refer to the PD78038, PD784038Y Sub-Series User's Manual, Hardware for details.
25
PD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (3/4)
Manipulatable bits AddressNote 1 0FF84H 0FF85H 0FF86H 0FF88H 0FF89H 0FF8AH 0FF8BH 0FF8CH Special function register (SFR) name Synchronous serial interface mode register 1 Synchronous serial interface mode register 2 Serial shift register Asynchronous serial interface mode register Asynchronous serial interface mode register 2 Asynchronous serial interface status register Asynchronous serial interface status register 2 Serial receive buffer: UART0 Serial transmission shift register: UART0 Serial shift register: IOE1 0FF8DH Serial receive buffer: UART2 Serial transmission shift register: UART2 Serial shift register: IOE2 0FF90H 0FF91H 0FFA0H 0FFA1H 0FFA4H 0FFA8H 0FFAAH 0FFACH 0FFADH 0FFAEH 0FFC0H 0FFC2H 0FFC4H 0FFC5H 0FFC6H 0FFC7H 0FFC8H Baud rate generator control register Baud rate generator control register 2 External interrupt mode register 0 External interrupt mode register 1 Sampling clock selection register In-service priority register Interrupt mode control register Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1L Standby control register Watchdog timer mode register Memory expansion mode register Hold mode register Clock output mode register Programmable wait control register 1 Programmable wait control register 2 Abbreviation CSIM1 CSIM2 SIO ASIM ASIM2 ASIS ASIS2 RXB TXS SIO1 RXB2 TXS2 SIO2 BRGC BRGC2 INTM0 INTM1 SCS0 ISPR IMC MK0L MK0 MK0H MK1L STBC WDM MM HLDM CLOM PWC1 PWC2 Note 2 Note 2
R/W 1 bit R/W 8 bits 16 bits R W R/W R W R/W R R/W -
When reset 00H
Undefined
00H
80H FFFFH
-
FFH 30H 00H 20H 00H
AAH AAAAH
Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address. 2. A write operation can be performed only with special instructions MOV STBC, #byte and MOV WDM,#byte. Other instructions cannot perform a write operation.
26
PD784035(A), 784036(A)
Table 6-1. Special Function Registers (SFRs) (4/4)
Manipulatable bits AddressNote 0FFCCH 0FFCDH 0FFCFH 0FFD0H0FFDFH 0FFE0H 0FFE1H 0FFE2H 0FFE3H 0FFE4H 0FFE5H 0FFE6H 0FFE7H 0FFE8H 0FFE9H 0FFEAH 0FFEBH 0FFECH 0FFEDH 0FFEEH 0FFEFH Interrupt control register (INTP0) Interrupt control register (INTP1) Interrupt control register (INTP2) Interrupt control register (INTP3) Interrupt control register (INTC00) Interrupt control register (INTC01) Interrupt control register (INTC10) Interrupt control register (INTC11) Interrupt control register (INTC20) Interrupt control register (INTC21) Interrupt control register (INTC30) Interrupt control register (INTP4) Interrupt control register (INTP5) Interrupt control register (INTAD) Interrupt control register (INTSER) Interrupt control register (INTSR) Interrupt control register (INTCSI1) 0FFF0H 0FFF1H 0FFF2H 0FFF3H Interrupt control register (INTST) Interrupt control register (INTCSI) Interrupt control register (INTSER2) Interrupt control register (INTSR2) Interrupt control register (INTCSI2) 0FFF4H Interrupt control register (INTST2) PIC0 PIC1 PIC2 PIC3 CIC00 CIC01 CIC10 CIC11 CIC20 CIC21 CIC30 PIC4 PIC5 ADIC SERIC SRIC CSIIC1 STIC CSIIC SERIC2 SRIC2 CSIIC2 STIC2 43H Special function register (SFR) name Refresh mode register Refresh area specification register Oscillation settling time specification register External SFR area Abbreviation RFM RFA OSTS R/W 1 bit R/W 8 bits 16 bits 00H When reset
Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H is added to each address.
27
PD784035(A), 784036(A)
7. PERIPHERAL HARDWARE FUNCTIONS
7.1 Ports
The ports shown in Figure 7-1 are provided to enable the application of wide-ranging control. Table 7-1 lists the functions of the ports. For the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software. Figure 7-1. Port Configuration
P00 Port 0 P07 P10 Port 1 P17
P20-P27
8
Port 2
P30 Port 3 P37 P40 Port 4 P47 P50 Port 5 P57 P60 Port 6 P67 P70 Port 7 P77
28
PD784035(A), 784036(A)
Table 7-1. Port Functions
Port name Port 0
Pin P00-P07
Function * Bit-by-bit input/output setting supported * Operable as 4-bit real-time outputs (P00-P03, P04-P07) * Capable of driving transistors
Pull-up specification by software Specified as a batch for all pins placed in input mode.
Port 1
P10-P17
* Bit-by-bit input/output setting supported * Capable of driving LEDs * Input port * Bit-by-bit input/output setting supported
Specified as a batch for all pins placed in input mode. Specified for the 6 bits (P22-P27) as a batch. Specified as a batch for all pins placed in input mode. Specified as a batch for all pins placed in input mode. Specified as a batch for all pins placed in input mode. Specified as a batch for all pins placed in input mode. -
Port 2 Port 3
P20-P27 P30-P37
Port 4
P40-P47
* Bit-by-bit input/output setting supported * Capable of driving LEDs * Bit-by-bit input/output setting supported * Capable of driving LEDs
Port 5
P50-P57
Port 6
P60-P67
* Bit-by-bit input/output setting supported
Port 7
P70-P77
* Bit-by-bit input/output setting supported
7.2
Clock Generator
A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed operation is not necessary. Figure 7-2. Block Diagram of Clock Generator
X1 Oscillator X2
fXX
1/2
1/2
1/2
1/2
Selector
fCLK CPU Peripheral circuits
fXX/2 UART/IOE INTP0 noise eliminator Oscillation settling timer
Remark fXX : Oscillator frequency or external clock input fCLK: Internal operating frequency
29
PD784035(A), 784036(A)
Figure 7-3. Examples of Using Oscillator (1) Crystal/ceramic oscillation
PD784036(A)
VSS1 X1
X2
(2) External clock * When EXTC bit of OSTS = 1 * When EXTC bit of OSTS = 0
PD784036(A)
X1
X1
PD784036(A)
PD74HC04, etc.
X2
Open
X2
Caution When using the clock generator, to avoid problems caused by influences such as stray capacitance, run all wiring within the area indicated by the dotted lines according to the following rules: * Minimize the wiring length. * Wires must never cross other signal lines. * Wires must never run near a line carrying a large varying current. * The grounding point of the capacitor of the oscillator must always be at the same potential as VSS1. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator.
30
PD784035(A), 784036(A)
7.3 Real-Time Output Port
The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. Thus, pulse output that is free of jitter can be obtained. Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals. As shown in Figure 7-4, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L). Figure 7-4. Block Diagram of Real-Time Output Port
Internal bus
8 Real-time output port control register (RTPC) INTP0 (externally) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1)
4 Buffer register P0H
4
8 P0L
Output trigger control circuit
4
4
Output latch (P0)
P07
P00
31
PD784035(A), 784036(A)
7.4 Timers/Counters
Three timer/counter units and one timer unit are incorporated. Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units. Table 7-2. Timer/Counter Operation
Name Item Count pulse width 8 bits 16 bits Operating mode Interval timer External event counter One-shot timer Function Timer output Toggle output PWM/PPG output One-shot pulse outputNote Real-time output Pulse width measurement Number of interrupt requests 1 input 2 1 input 2 2ch 2 inputs 2 2ch 2ch 2ch 2ch 1ch 1
Timer/counter 0 -
Timer/counter 1
Timer/counter 2
Timer 3
Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the level of a pulse output inactive by hardware (interrupt request signal). Note that this function differs from the one-shot timer function of timer/counter 2.
32
PD784035(A), 784036(A)
Figure 7-5. Timer/Counter Block Diagram Timer/counter 0
Clear information
Software trigger
Selector
fxx/8
Prescaler
Timer register 0 (TM0)
Compare register (CR00)
OVF
Pulse output control
Match Match
TO0
Compare register (CR01)
TO1
INTP3
Edge detection
Capture register (CR02)
INTP3
INTC00 INTC01
Timer/counter 1
Clear information
Selector
fxx/8
Prescaler Event input
Timer register 1 (TM1/TM1W)
OVF
Match
Compare register (CR10/CR10W)
INTP0
Edge detection
Capture/compare register (CR11/CR11W)
Match
INTC10 To real-time output port INTC11
INTP0
Capture register (CR12/CR12W)
Timer/counter 2
Clear information
Selector
fxx/8
Prescaler
Timer register 2 (TM2/TM2W)
OVF
Pulse output control
Match
INTP2/CI
Edge detection
Compare register (CR20/CR20W)
TO2
INTP2
Capture/compare register (CR21/CR21W)
Match
TO3
INTP1
Edge detection
Capture register (CR22/CR22W)
INTC20 INTC21
INTP1
Timer 3
fxx/8 Prescaler
Timer register 3 (TM3/TM3W)
Clear
Compare register (CR30/CR30W)
Match
CSI INTC30
Remark OVF: Overflow flag
33
PD784035(A), 784036(A)
7.5 PWM Output (PWM0, PWM1)
Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 62.5 kHz (fCLK = 16 MHz) are incorporated. Low or high active level can be selected for the PWM output channels, independently of each other. This output is best suited to DC motor speed control. Figure 7-6. Block Diagram of PWM Output Unit
Internal bus 16 PWM modulo register PWMn 15 8 87 4 Reload control 43 0 8 PWM control register (PWMC)
fCLK
Prescaler
8-bit down-counter
Pulse control circuit 4-bit counter
Output control
PWMn (output pin)
1/256
Remark n = 0, 1
34
PD784035(A), 784036(A)
7.6 A/D Converter
An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated. The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. (The conversion time is about 7.5 s at fCLK = 16 MHz.) A/D conversion can be started in any of the following modes: * Hardware start : Conversion is started by means of trigger input (INTP5). * Software start : Conversion is started by means of bit setting the A/D converter mode register (ADM). After conversion has started, one of the following modes can be selected: * Scan mode : Multiple analog inputs are selected sequentially to obtain conversion data from all pins. * Select mode: A single analog input is selected at all times to enable conversion data to be obtained continuously. ADM is used to specify the above modes, as well as the termination of conversion. When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature, the results of conversion can be continuously transferred to memory by the macro service. Figure 7-7. Block Diagram of A/D Converter
ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7
Input selector
Sample-and-hold circuit
Series resistor string AVREF1 Voltage comparator R/2 R
Successive conversion register (SAR) Edge detector Conversion trigger INTAD
INTP5
Control circuit
Tap selector R/2 AVSS
Trigger enable 8 A/ D converter mode register (ADM) A/ D conversion result register (ADCR)
8
8
Internal bus
35
PD784035(A), 784036(A)
7.7 D/A Converter
Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated. An R-2R resistor ladder system is used for conversion. By writing the value to be subject to D/A conversion in the 8-bit D/A conversion value setting register (DACSn: n = 0, 1), the resulting analog value is output on ANOn (n = 0, 1). The range of the output voltages is determined by the voltages applied to the AVREF2 and AVREF3 pins. Because of its high output impedance, no current can be obtained from an output pin. When the load impedance is low, insert a buffer amplifier between the load and the converter. The impedance of the ANOn pin goes high while the RESET signal is low. DACSn is set to 0 after a reset is released. Figure 7-8. Block Diagram of D/A Converter
ANOn 2R AVREF2 R
2R
Selector
R
AVREF3
2R R
2R
DACSn
DACEn
Internal bus
Remark
n = 0, 1
36
PD784035(A), 784036(A)
7.8 Serial Interface
Three independent serial interface channels are incorporated.
* Asynchronous serial interface (UART)/three-wire serial I/O (IOE) x 2 * Synchronous serial interface (CSI) x 1
* Three-wire serial I/O (IOE) * Two-wire serial I/O (IOE) So, communication with points external to the system and local communication within the system can be performed at the same time. (See Figure 7-9.) Figure 7-9. Example Serial Interfaces
UART + Three-wire serial I/O + Two-wire serial I/O
PD784036(A)
Master
[UART]
Slave [Three-wire serial I/O] SI SO SCK Port INT VDD VDD Slave
RS-232-C driver/receiver
RxD TxD Port
SO1 SI1 SCK1 INTPm Port
Note
SDA SCL INTPn Port [Two-wire serial I/O]
Note
SB0 SCK0 Port INT
Note Handshake line
37
PD784035(A), 784036(A)
7.8.1 Asynchronous serial interface/three-wire serial I/O (UART/IOE)
Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial I/O mode can be selected. (1) Asynchronous serial interface mode In this mode, 1-byte data is transferred after a start bit. A baud rate generator is incorporated to enable communication at a wide range of baud rates. Moreover, the frequency of a clock signal applied to the ASCK pin can be divided to define a baud rate. With the baud rate generator, the baud rate conforming to the MIDI standard (31.25 kbps) can be obtained. Figure 7-10. Block Diagram of Asynchronous Serial Interface Mode
Internal bus
Receive buffer
RXB, RXB2
RxD, RxD2
Receive shift register
Transmission shift register
TXS, TXS2
TxD, TxD2 INTSR, INTSR2 INTSER, INTSER2
Reception control parity check
Transmission control parity bit addition
INTST, INTST2
Baud rate generator
1/2m fXX/2 ASCK, ASCK2
Selector
1/2n+1 1/2m
Remark fXX: Oscillator frequency or external clock input n = 0 to 11 m = 16 to 30
38
PD784035(A), 784036(A)
(2) Three-wire serial I/O mode In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI and SO). In general, a handshake line is required to check the state of communication. Figure 7-11. Block Diagram of Three-Wire Serial I/O Mode
Internal bus
Direction control circuit
SIO1, SIO2 SI1, SI2 Shift register Output latch
SO1, SO2
SCK1, SCK2
Serial clock counter
Interrupt signal generator
INTCSI1, INTCSI2
Serial clock control circuit
Remark fXX: Oscillator frequency or external clock input n = 0 to 11 m = 1, 16 to 30
Selector
1/m
1/2n+1
fXX/2
39
PD784035(A), 784036(A)
7.8.2 Synchronous serial interface (CSI)
With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. Figure 7-12. Block Diagram of Synchronous Serial Interface
Internal bus
Direction control circuit
Set
Reset
Selector
SI0 SO0/SDA
Shift register
Output latch
N-ch open-drain output enabled (when two-wire mode is used) SCK0/SCL Serial clock counter Interrupt signal generator INTCSI
Prescaler
Selector
N-ch open-drain output enabled (when two-wire mode is used) CLS0 CLS1
Selector
Serial clock control circuit
Timer 3 output fXX/16
fXX/2
Remark fXX: Oscillator frequency or external clock input
40
PD784035(A), 784036(A)
(1) Three-wire serial I/O mode This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0). In general, a handshake line is required to check the state of communication. (2) Two-wire serial I/O mode In this mode, 8-bit data is transferred using two lines: the serial clock line (SCL) and serial data bus (SDA). In general, a handshake line is required to check the communication state. 7.9 Clock Output Function
The frequency of the CPU clock signal can be divided for output to a point external to the system. Moreover, the port can be used as a 1-bit port. The ASTB pin is also used for the CLKOUT pin, so that when this function is used, the local bus interface cannot be used. Figure 7-13. Block Diagram of Clock Output Function
fCLK fCLK/2
Selector
fCLK/4 fCLK/8 fCLK/16
Output control
CLKOUT
Enable output
Output level
41
PD784035(A), 784036(A)
7.10 Edge Detection Function
The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals for the built-in circuits. As these pins are triggered by an edge (rising or falling) of an input signal, a function for edge detection is incorporated. Moreover, a noise suppression function is provided to prevent erroneous edge detection caused by noise. Table 7-3. Noise Suppression Method for Interrupt Input Pins
Pin NMI INTP0-INTP3 INTP4, INTP5 Detectable edge Rising edge or falling edge Rising edge or falling edge, or both edges Noise suppression method Analog delay Clock samplingNote Analog delay
Note INTP0 is used for sampling clock selection.
7.11 Watchdog Timer A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. The user can specify whether priority is placed on an interrupt based on the watchdog timer or on an interrupt based on the NMI pin. Figure 7-14. Block Diagram of Watchdog Timer
fCLK
Timer fCLK/221 fCLK/220
Selector
fCLK/219 fCLK/217
INTWDT
Clear signal
42
PD784035(A), 784036(A)
8. INTERRUPT FUNCTION
Table 8-1 lists the interrupt request handling modes. These modes are selected by software. Table 8-1. Interrupt Request Handling Modes
Handling mode Vectored interrupt
Handled by Software
Handling Branches to a handling routine for execution (arbitrary handling). Automatically selects a register bank, and branches to a handling routine for execution (arbitrary handling).
PC and PSW contents The PC and PSW contents are pushed to and popped from the stack. The PC and PSW contents are saved to and read from a fixed area in the register bank. Maintained
Context switching
Macro service
Firmware
Performs operations such as memory-to-I/Odevice data transfer (fixed handling).
8.1
Interrupt Source
An interrupt can be issued from any one of the interrupt sources listed in Table 8-2: execution of BRK and BRKCS instructions, an operand error, or any of the 23 other interrupt sources. Four levels of interrupt handling priority can be set. Priority levels can be set to nest control during interrupt handling or to concurrently generate interrupt requests. Nested macro services, however, are performed without suspension. When interrupt requests having the same priority level are generated, they are handled according to the default priority (fixed). (See Table 8-2.)
43
PD784035(A), 784036(A)
Table 8-2. Interrupt Sources
Type
Default priority Name BRK instruction BRKCS instruction Operand error
Source Trigger Instruction execution
Internal/ external -
Macro service -
Software
When the MOV STBC,#byte, MOV WDM,#byte, or LOCATION instruction is executed, exclusive OR of the byte operand and byte does not produce FFH. Detection of edge input on the pin Watchdog timer overflow Detection of edge input on the pin (TM1/TM1W capture trigger, TM1/TM1W event counter input) Detection of edge input on the pin (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection of edge input on the pin (TM2/TM2W capture trigger, TM2/TM2W event counter input) Detection of edge input on the pin (TM0 capture trigger, TM0 event counter input) TM0-CR00 match signal issued TM0-CR01 match signal issued TM1-CR10 match signal issued (in 8-bit operation mode) TM1W-CR10W match signal issued (in 16-bit operation mode) TM1-CR11 match signal issued (in 8-bit operation mode) TM1W-CR11W match signal issued (in 16-bit operation mode) TM2-CR20 match signal issued (in 8-bit operation mode) TM2W-CR20W match signal issued (in 16-bit operation mode) TM2-CR21 match signal issued (in 8-bit operation mode) TM2W-CR21W match signal issued (in 16-bit operation mode) TM3-CR30 match signal issued (in 8-bit operation mode) TM3W-CR30W match signal issued (in 16-bit operation mode) Detection of edge input on the pin Detection of edge input on the pin A/D converter processing completed (ADCR transfer) ASI0 reception error ASI0 reception completed or CSI1 transfer completed Internal Enabled Enabled External Enabled Internal Enabled External Internal External Enabled -
Nonmaskable
-
NMI WDT
Maskable
0 (highest)
INTP0
1
INTP1
2
INTP2
3
INTP3
4 5 6
INTC00 INTC01 INTC10
7
INTC11
8
INTC20
9
INTC21
10
INTC30
11 12 13 14 15
INTP4 INTP5 INTAD INTSER INTSR INTCSI1
16 17 18 19
INTST INTCSI INTSER2 INTSR2 INTCSI2
ASI0 transmission completed CSI0 transfer completed ASI2 reception error ASI2 reception completed or CSI2 transfer completed Enabled
20 (lowest)
INTST2
ASI2 transmission completed
Remark ASI: Asynchronous serial interface CSI: Synchronous serial interface
44
PD784035(A), 784036(A)
8.2 Vectored Interrupt
When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. Interrupt handling by the CPU consists of the following operations: * When a branch occurs : Push the CPU status (PC and PSW contents) to the stack.
* When control is returned : Pop the CPU status (PC and PSW contents) from the stack. To return control from the handling routine to the main routine, use the RETI instruction. The branch destination addresses must be within the range of 0 to FFFFH. Table 8-3. Vector Table Address
Interrupt source BRK instruction Operand error NMI WDT INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC20 INTC21 INTC30 INTP4 INTP5 INTAD INTSER INTSR INTCSI1 INTST INTCSI INTSER2 INTSR2 INTCSI2 INTST2
Vector table address 003EH 003CH 0002H 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH 0020H 0022H 0024H
0026H 0028H 002AH 002CH
002EH
45
PD784035(A), 784036(A)
8.3 Context Switching
When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register bank. The branch address must be within the range of 0 to FFFFH. Figure 8-1. Context Switching Caused by an Interrupt Request
0000B <7> Transfer PC19-16 PC15-0 <6> Exchange Register bank n (n = 0-7) A B <2> Save (Bits 8 to 11 of temporary register) R5 R7 <5> Save Temporary register <1> Save PSW V U T W D H VP UP E L <3> Switching between register banks (RBS0-RBS2 n) <4> RSS 0 IE 0 X C R4 R6 Register bank (0-7)
8.4
Macro Service
The macro service function enables data transfer between memory and special function registers (SFRs) without requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same transfer cycle to directly transfer data without having to perform data fetch. Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible. Figure 8-2. Macro Service
Read CPU Memory Write
Macro service controller
Write SFR Read
Internal bus
46
PD784035(A), 784036(A)
8.5 Examples of Macro Service Applications
(1) Serial interface transmission
Transmission data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Internal bus
TxD
Transmission shift register
TXS (SFR)
Transmission control
INTST
Each time a macro service request (INTST) is generated, the next transmission data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmission data storage buffer becomes empty), a vectored interrupt request (INTST) is generated. (2) Serial interface reception
Reception data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Internal bus
Reception buffer
RXB (SFR)
RxD
Reception shift register
Reception control
INTSR
Each time a macro service request (INTSR) is generated, reception data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full), a vectored interrupt request (INTSR) is generated.
47
PD784035(A), 784036(A)
(3) Real-time output port INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used to independently control two stepping motors. They can also be applied to PWM and DC motor control.
Output pattern profile (memory) Pn Pn-1 Output timing profile (memory) Tn Tn-1
P2 P1
T2 T1
Internal bus
Internal bus
Match (SFR) P0L INTC10 Output latch P00-P03 TM1 CR10 (SFR)
Each time a macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10 match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last byte) is transferred to CR10, a vectored interrupt request (INTC10) is generated. For INTC11, the same operation as that performed for INTC10 is performed.
48
PD784035(A), 784036(A)
9. LOCAL BUS INTERFACE
The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It supports a 1M-byte memory space. (See Figure 9-1.) Figure 9-1. Example of Local Bus Interface
PD784036(A)
A16-A19
RD WR REFRQ
Decoder
Pseudo SRAM
PROM PD27C1001A
Kanji character generator PD24C1000
AD0-AD7
Data bus Data bus
ASTB
Latch
Address bus A8-A15 Gate array for I/O expansion including Centronics interface circuit, etc.
9.1
Memory Expansion
By adding external memory, program memory or data memory can be expanded to one of seven sizes between 256 bytes and approximately 1M byte.
49
PD784035(A), 784036(A)
9.2 Memory Space
The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces can be controlled using the programmable wait and pseudo-static RAM refresh functions. Figure 9-2. Memory Space
FFFFFH
512K bytes
80000H 7FFFFH 256K bytes 40000H 3FFFFH 128K bytes 20000H 1FFFFH 64K bytes 10000H 0FFFFH 16K bytes 0C000H 0BFFFH 16K bytes 08000H 07FFFH 16K bytes 04000H 03FFFH 16K bytes 00000H
50
PD784035(A), 784036(A)
9.3 Programmable Wait
When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when memory devices having different access times are connected. In addition, an address wait function that extends the ASTB signal active period is provided to assure a longer address decode time. (This function is set for the entire space.) 9.4 Pseudo-Static RAM Refresh Function
Refresh is performed as follows: * Pulse refresh A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal memory access. * Power-down self-refresh In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM. 9.5 Bus Hold Function
A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus cycle being performed at the reception, the address bus, address/data bus, ASTB, RD, and WR pins are placed in the high-impedance state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the external bus master. While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.
51
PD784035(A), 784036(A)
10. STANDBY FUNCTION
The standby function allows the power consumption of the chip to be reduced. The following standby modes are supported: * HALT mode : The CPU operation clock is stopped. By occasionally inserting the HALT mode during normal operation, the overall average power consumption can be reduced. * IDLE mode : The entire system is stopped, with the exception of the oscillator. This mode consumes only very little more power than STOP mode, but normal program operation can be restored in almost as little time as that required to restore normal program operation from HALT mode. * STOP mode : The oscillator is stopped. All operations in the chip stop, such that only leakage current flows. These modes can be selected by software. A macro service can be initiated in HALT mode. Figure 10-1. Standby Mode Status Transition
Macro service request Program operation End of one operation End of macro service Macro service
Wait for oscillation settling
1 e ot
ttling tion se Oscilla ses p time ela
Int
N t es qu t re u pt inp ru T LT er SE HA RE Set
1
TP
IN
M
NM
I,
NM
I,
STOP (standby)
IDLE (standby)
Request for masked interrupt
HALT (standby)
Notes 1. INTP4 and INTP5 are applied when not masked. 2. Only when the interrupt request is not masked Remark NMI is enabled only by external input. The watchdog timer cannot be used to release one of the standby modes (STOP, HALT, or IDLE mode).
52
En
d
P TO ut t S inp Se ET S RE
S R et IN ESE IDL TP T E 4, in IN pu TP t 5 inp
4,
ro ac
of
se rv i on ce r e e op qu e er at st ion
ut N
IN
TP
5
inp
ut No
te
ot e2
PD784035(A), 784036(A)
11. RESET FUNCTION
Applying a low-level signal to the RESET pin initializes the internal hardware (reset status). When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC): * Eight low-order bits of the PC * Four high-order bits of the PC : Contents of location at address 0000H :0
* Intermediate eight bits of the PC : Contents of location at address 0001H
The PC contents are used as a branch destination address. Program execution starts from that address. Therefore, a reset start can be performed from an arbitrary address. The contents of each register can be set by software, as required. The RESET input circuit contains a noise eliminator to prevent malfunctions caused by noise. This noise eliminator is an analog delay sampling circuit. Figure 11-1. Accepting a Reset
Delay
Delay
Delay
Initialize PC
Execute instruction at reset start address
RESET (input)
Internal reset signal
Start reset
End reset
For power-on reset, the RESET signal must be held active until the oscillation settling time (approximately 40 ms) has elapsed. Figure 11-2. Power-On Reset
Oscillation settling time
Delay
Initialize PC
Execute instruction at reset start address
VDD
RESET (input)
Internal reset signal
End reset
53
PD784035(A), 784036(A)
12. INSTRUCTION SET
(1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where A is described as r.) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 12-1. Instructions Implemented by 8-Bit Addressing
2nd operand
#byte
A
r r'
saddr saddr'
sfr
!addr16 !!addr24
mem [saddrp] [%saddrg]
r3 PSWL PSWH MOV
[WHL+] [WHL-]
n
NoneNote 2
1st operand A (MOV) ADDNote 1 (MOV) (XCH) MOV XCH (MOV)Note 6 MOV (XCH)Note 6 (XCH) (MOV) (XCH)
MOV XCH
(MOV) (XCH) (ADD)Note 1 RORNote 3 MULU DIVUW INC DEC
(ADD)Note 1 (ADD)Note 1 (ADD)Notes 1, 6 (ADD)Note 1 ADDNote 1 ADDNote 1 r MOV ADDNote 1 (MOV) (XCH) MOV XCH MOV XCH ADDNote 1 MOV XCH ADDNote 1 MOV XCH
(ADD)Note 1 ADDNote 1
saddr
MOV
(MOV)Note 6
MOV
MOV XCH ADDNote 1
INC DEC DBNZ PUSH POP CHKL CHKLA
ADDNote 1 (ADD)Note 1 ADDNote 1
sfr
MOV
MOV
MOV
ADDNote 1 (ADD)Note 1 ADDNote 1
!addr16 !!addr24 mem [saddrp] [%saddrg] mem3
MOV
(MOV) ADDNote 1 MOV ADDNote 1
MOV
ROR4 ROL4
r3 PSWL PSWH B, C STBC, WDM [TDE+] [TDE-]
MOV
MOV
DBNZ MOV (MOV) (ADD)Note 1 MOVMNote 4 MOVBKNote 5
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. There is no second operand, or the second operand is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. When saddr is saddr2 with this combination, an instruction with a short code exists.
54
PD784035(A), 784036(A)
(2) 16-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where AX is described as rp.) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instructions Implemented by 16-Bit Addressing
2nd operand
#word
AX
rp rp'
saddrp saddrp'
strp
!addr16 !!addr24
mem [saddrp] [%saddrg]
[WHL+]
byte
n
NoneNote 2
1st operand AX (MOVW) (MOVW) (MOVW) (XCHW) (MOVW)Note 3 MOVW (MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
ADDWNote 1 (XCHW)
(XCHW)Note 3 (XCHW)
(ADD)Note 1 (ADDW)Note 1 (ADDW)Notes 1,3 (ADDW)Note 1 rp MOVW (MOVW) MOVW XCHW MOVW XCHW MOVW XCHW MOVW SHRW SHLW MULWNote 4 INCW DECW INCW DECW
ADDWNote 1 (XCHW)
(ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 saddrp MOVW (MOVW)Note 3 MOVW MOVW ADDWNote 1 sfrp MOVW MOVW MOVW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 XCHW
PUSH POP MOVTBLW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW
PUSH POP
SP
ADDWG SUBWG
post
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. SUBW and CMPW are the same as ADDW. 2. There is no second operand, or the second operand is not an operand address. 3. When saddrp is saddrp2 with this combination, an instruction with a short code exists. 4. MULUW and DIVUX are the same as MULW.
55
PD784035(A), 784036(A)
(3) 24-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where WHL is described as rg.) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instructions Implemented by 24-Bit Addressing
2nd operand 1st operand WHL
#imm24
WHL
rg rg'
saddrg
!!addr24
mem1
[%saddrg]
SP
NoneNote
(MOVG) (ADDG) (SUBG)
(MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG)
(MOVG) (ADDG) (SUBG) MOVG ADDG SUBG
(MOVG) ADDG SUBG MOVG
(MOVG)
MOVG
MOVG
MOVG
rg
MOVG ADDG SUBG
MOVG
INCG DECG PUSH POP
saddrg !!addr24 mem1 [%saddrg] SP MOVG
(MOVG) (MOVG) MOVG MOVG MOVG
MOVG MOVG
INCG DECG
Note There is no second operand, or the second operand is not an operand address.
56
PD784035(A), 784036(A)
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 12-4. Bit Manipulation Instructions Implemented by Addressing
2nd operand
CY
saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit
/saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit AND1 OR1 /!!addr24.bit
NoneNote
1st operand CY
!addr16.bit !!addr24.bit MOV1 AND1 OR1 XOR1
NOT1 SET1 CLR1
saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit
MOV1
NOT1 SET1 CLR1 BF BT BTCLR BFSET
Note There is no second operand, or the second operand is not an operand address.
57
PD784035(A), 784036(A)
(5) Call/return instructions and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Call/Return and Branch Instructions Implemented by Addressing
Instruction address operand Basic instruction
$addr20 $!addr20
!addr16
!!addr20
rp
rg
[rp]
[rg]
!addr11
[addr5]
RBn
None
BCNote BR
CALL BR
CALL BR RETCS RETCSB
CALL BR
CALL BR
CALL BR
CALL BR
CALL BR
CALLF
CALLF
BRKCS
BRK RET RETI RETB
Composite BF instruction BT BTCLR BFSET DBNZ
Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT EI, DI, SWRS
58
PD784035(A), 784036(A)
13. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVSS Input voltage Output voltage Output low current VI VO IOL At one pin Total of all output pins Output high current IOH At one pin Total of all output pins A/D converter reference input voltage D/A converter reference input voltage Operating ambient temperature Storage temperature AVREF1 Conditions Rating -0.5 to +7.0 AVSS to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 15 100 -10 -100 -0.5 to VDD + 0.3 Unit V V V V V mA mA mA mA V
AVREF2 AVREF3 TA Tstg
-0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150
V V C C
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. Always use the product within its rated values.
59
PD784035(A), 784036(A)
OPERATING CONDITIONS * Operating ambient temperature (TA) * Power supply voltage and clock cycle time : -40 to +85 C : See Figure 13-1. * Rise time and fall time (tr, tf) (at pins which are not specified) : 0 to 200 s
Figure 13-1. Power Supply Voltage and Clock Cycle Time
10 000 4 000
Clock cycle time tCYK [ns]
1 000 Guaranteed operating range 125 100 62.5
10
0
1
2 3 4 5 Power supply voltage [V]
6
7
CAPACITANCE (TA = 25 C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO f = 1 MHz 0 V on pins other than measured pins Conditions MIN. TYP. MAX. 10 10 10 Unit pF pF pF
60
PD784035(A), 784036(A)
OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = +4.5 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal Recommended circuit Parameter Oscillator frequency (fXX) MIN. 4 MAX. 32 Unit MHz
VSS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
32
MHz
X1
X2
X1 input rise and fall times (tXR, tXF) X1 input high-level and lowlevel widths (tWXH, tWXL)
0
10
ns
10
125
ns
HCMOS inverter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: * Minimize the wiring. * Never cause the wires to cross other signal lines. * Never cause the wires to run near a line carrying a large varying current. * Cause the grounding point of the capacitor of the oscillator to have the same potential as VSS1. Never connect the capacitor to a ground pattern carrying a large current. * Never extract a signal from the oscillator.
61
PD784035(A), 784036(A)
OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = +2.7 to 5.5 V, VSS = 0 V)
Resonator Ceramic resonator or crystal Recommended circuit Parameter Oscillator frequency (fXX) MIN. 4 MAX. 16 Unit MHz
VSS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
16
MHz
X1
X2
X1 input rise and fall times (tXR, tXF) X1 input high-level and lowlevel widths (tWXH, tWXL)
0
10
ns
10
125
ns
HCMOS inverter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: * * * * * Minimize the wiring. Never cause the wires to cross other signal lines. Never cause the wires to run near a line carrying a large varying current. Cause the grounding point of the capacitor of the oscillator to have the same potential as VSS1. Never connect the capacitor to a ground pattern carrying a large current. Never extract a signal from the oscillator.
62
PD784035(A), 784036(A)
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter Input low voltage Symbol VIL1 Conditions For pins other than those described in Notes 1, 2, 3, and 4 For pins described in Notes 1, 2, 3, and 4 VDD = +5.0 V 10 % For pins described in Notes 2, 3, and 4 For pins other than those described in Note 1 For pins described in Note 1 VDD = +5.0 V 10 % For pins described in Notes 2, 3, and 4 IOL = 2 mA VDD = +5.0 V 10 % IOL = 8 mA For pins described in Notes 2 and 5 IOH = -2 mA VDD = +5.0 V 10 % IOH = -5 mA For pins described in Note 4 EXTC = 0 0 V VI VIL2 EXTC = 0 VIH2 VI VDD VDD - 1.0 VDD - 1.4 MIN. -0.3 TYP. MAX. 0.3VDD Unit V
VIL2
-0.3
0.2VDD
V
VIL3
-0.3
+0.8
V
Input high voltage
VIH1
0.7VDD
VDD + 0.3
V
VIH2 VIH3
0.8VDD 2.2
VDD + 0.3 VDD + 0.3
V V
Output low voltage
VOL1 VOL2
0.4 1.0
V V
Output high voltage
VOH1 VOH2
V V
X1 input low current
IIL
-30
A A
X1 input high current
IIH
+30
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA, TEST 2. P40/AD0-P47/AD7, P50/A8-P57/A15 3. P60/A16-P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK 4. P00-P07 5. P10-P17
63
PD784035(A), 784036(A)
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter Input leakage current Symbol ILI Conditions 0 V VI VDD For pins other than X1 when EXTC = 0 0 V VO VDD Operation mode fXX = 32 MHz VDD = +5.0 V 10 % fXX = 16 MHz VDD = +2.7 to 3.3 V IDD2 HALT mode fXX = 32 MHz VDD = +5.0 V 10 % fXX = 16 MHz VDD = +2.7 to 3.3 V IDD3 IDLE mode (EXTC = 0) fXX = 32 MHz VDD = +5.0 V 10 % fXX = 16 MHz VDD = +2.7 to 3.3 V Pull-up resistor RL VI = 0 V 15 25 MIN. TYP. MAX. 10 10 45 Unit
A A
mA
Output leakage current VDD supply current
ILO IDD1
12
25
mA
13
26
mA
8
12
mA
12
mA
8
mA
80
k
64
PD784035(A), 784036(A)
AC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1) Read/write operation (1/2)
Parameter Address setup time Symbol tSAST Conditions VDD = +5.0 V 10 % MIN. (0.5 + a) T - 15 (0.5 + a) T - 31 ASTB high-level width tWSTH VDD = +5.0 V 10 % (0.5 + a) T - 17 (0.5 + a) T - 40 Address hold time (to ASTB) tHSTLA VDD = +5.0 V 10 % 0.5T - 24 0.5T - 34 Address hold time (to RD) Delay from address to RD tHRA tDAR VDD = +5.0 V 10 % 0.5T - 14 (1 + a) T - 9 (1 + a) T - 15 Address float time (to RD) tFRA VDD = +5.0 V 10 % 0 (2.5 + a + n) T - 37 (2.5 + a + n) T - 52 Delay from ASTB to data input tDSTID VDD = +5.0 V 10 % (2 + n) T - 40 (2 + n) T - 60 Delay from RD to data input tDRID VDD = +5.0 V 10 % (1.5 + n) T - 50 (1.5 + n) T - 70 Delay from ASTB to RD Data hold time (to RD) tDSTR tHRID After program is read After data is read Delay from RD to ASTB RD low-level width tDRST tWRL VDD = +5.0 V 10 % VDD = +5.0 V 10 % 0.5T - 9 0 0.5T - 8 0.5T - 12 VDD = +5.0 V 10 % 1.5T - 8 1.5T - 12 0.5T - 17 (1.5 + n) T - 30 (1.5 + n) T - 40 Address hold time (to WR) Delay from address to WR tHWA tDAW VDD = +5.0 V 10 % 0.5T - 14 (1 + a) T - 5 (1 + a) T - 15 Delay from ASTB to data output tDSTOD VDD = +5.0 V 10 % 0.5T + 19 0.5T + 35 Delay from WR to data output Delay from ASTB to WR tDWOD tDSTW 0.5T - 9 0.5T - 11 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Delay from address to data input tDAID
Delay from RD to address active tDRA
Remarks T: TCYK (system clock cycle time) a: n: 1 (during address wait), otherwise, 0 Number of wait states (n 0)
65
PD784035(A), 784036(A)
(1) Read/write operation (2/2)
Parameter Data setup time (to WR) Symbol tSODW Conditions VDD = +5.0 V 10 % MIN. (1.5 + n) T - 30 (1.5 + n) T - 40 Data hold time (to WR)Note tHWOD VDD = +5.0 V 10 % 0.5T - 5 0.5T - 25 Delay from WR to ASTB WR low-level width tDWST tWWL VDD = +5.0 V 10 % 0.5T - 12 (1.5 + n) T - 30 (1.5 + n) T - 40 MAX. Unit ns ns ns ns ns ns ns
Note The hold time includes the time during which VOH1 and VOL1 are held under the load conditions of CL = 50 pF and RL = 4.7 k. Remarks T: TCYK (system clock cycle time) n: Number of wait states (n 0)
(2) Bus hold timing
Parameter Delay from HLDRQ to float Symbol tFHQC VDD = +5.0 V 10 % Conditions MIN. MAX. (6 + a + n) T + 50 (7 + a + n) T + 30 (7 + a + n) T + 40 Delay from float to HLDAK tDCFHA VDD = +5.0 V 10 % 1T + 30 2T + 40 2T + 60 Delay from HLDAK to active tDHAC VDD = +5.0 V 10 % 1T - 20 1T - 30 Unit ns ns ns ns ns ns ns ns
Delay from HLDRQ to HLDAK tDHQHHAH
Delay from HLDRQ to HLDAK tDHQLHAL
Remarks T: TCYK (system clock cycle time) a: n: 1 (during address wait), otherwise, 0 Number of wait states (n 0)
66
PD784035(A), 784036(A)
(3) External wait timing
Parameter Symbol Conditions VDD = +5.0 V 10 % MIN. MAX. (2 + a) T - 40 (2 + a) T - 60 Delay from ASTB to WAIT input tDSTWT VDD = +5.0 V 10 % 1.5T - 40 1.5T - 60 Hold time from ASTB to WAIT tHSTWTH VDD = +5.0 V 10 % (0.5 + n) T + 5 (0.5 + n) T +10 Delay from ASTB to WAIT tDSTWTH VDD = +5.0 V 10 % (1.5 + n) T - 40 (1.5 + n) T - 60 Delay from RD to WAIT input tDRWTL VDD = +5.0 V 10 % T - 50 T - 70 Hold time from RD to WAIT tHRWT VDD = +5.0 V 10 % nT + 5 nT + 10 Delay from RD to WAIT tDRWTH VDD = +5.0 V 10 % (1 + n) T - 40 (1 + n) T - 60 Delay from WAIT to data input tDWTID VDD = +5.0 V 10 % 0.5T - 5 0.5T - 10 Delay from WAIT to WR Delay from WAIT to RD tDWTW tDWTR VDD = +5.0 V 10 % 0.5T 0.5T T - 50 T - 75 Hold time from WR to WAIT tHWWT VDD = +5.0 V 10 % nT + 5 nT + 10 Delay from WR to WAIT tDWWTH VDD = +5.0 V 10 % (1 + n) T - 40 (1 + n) T - 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Delay from address to WAIT input tDAWT
Delay from WR to WAIT input tDWWTL
Remarks T: TCYK (system clock cycle time) a: n: 1 (during address wait), otherwise, 0 Number of wait states (n 0)
(4) Refresh timing
Parameter Random read/write cycle time REFRQ low-level pulse width Symbol tRC tWRFQL VDD = +5.0 V 10 % Conditions MIN. 3T 1.5T - 25 1.5T - 30 Delay from ASTB to REFRQ Delay from RD to REFRQ Delay from WR to REFRQ Delay from REFRQ to ASTB REFRQ high-level pulse width tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH VDD = +5.0 V 10 % 0.5T - 9 1.5T - 9 1.5T - 9 0.5T - 15 1.5T - 25 1.5T - 30 MAX. Unit ns ns ns ns ns ns ns ns ns
Remark T: TCYK (system clock cycle time)
67
PD784035(A), 784036(A)
SERIAL OPERATION (TA = -40 to +85 C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V) (1) CSI
Parameter Symbol Input Conditions External clock When SCK0 and SO0 are CMOS I/O MIN. 10/fXX + 380 MAX. Unit ns
Serial clock cycle time (SCK0) tCYSK0
Output Serial clock low-level width (SCK0) tWSKL0 Input External clock When SCK0 and SO0 are CMOS I/O
T 5/fXX + 150
s
ns
Output Serial clock high-level width (SCK0) tWSKH0 Input External clock When SCK0 and SO0 are CMOS I/O
0.5T - 40 5/fXX + 150
s
ns
Output SI0 setup time (to SCK0) SI0 hold time (to SCK0) SO0 output delay time (to SCK0) tSSSK0 tHSSK0 tDSBSK1 CMOS push-pull output (3-wire serial I/O mode) Open-drain output (2-wire serial I/O mode), RL = 1 k
0.5T - 40 40 5/fXX + 40 0 5/fXX + 150
s
ns ns ns
tDSBSK2
0
5/fXX + 400
ns
Remarks 1. The values in this table are those when CL is 100 pF. 2. T : Serial clock cycle set by software. The minimum value is 16/fXX. Oscillator frequency 3. fXX :
68
PD784035(A), 784036(A)
(2) IOE1, IOE2
Parameter Serial clock cycle time (SCK1, SCK2) Symbol tCYSK1 Input Conditions VDD = +5.0 V 10 % MIN. 250 500 Output Serial clock low-level width (SCK1, SCK2) tWSKL1 Input Internal, divided by 16 VDD = +5.0 V 10 % T 85 210 Output Serial clock high-level width (SCK1, SCK2) tWSKH1 Input Internal, divided by 16 VDD = +5.0 V 10 % 0.5T - 40 85 210 Output Setup time for SI1 and SI2 (to SCK1, SCK2) Hold time for SI1 and SI2 (to SCK1, SCK2) tSSSK1 Internal, divided by 16 0.5T - 40 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns
tHSSK1
40
ns
Output delay time for SO1 and tDSOSK SO2 (to SCK1, SCK2) Output hold time for SO1 and SO2 (to SCK1, SCK2) tHSOSK When data is transferred
0
50
ns
0.5tCYSK1 - 40
ns
Remarks 1. The values in this table are those when CL is 100 pF. 2. T: Serial clock cycle set by software. The minimum value is 16/fXX. (3) UART, UART2
Parameter ASCK clock input cycle time Symbol tCYASK Conditions VDD = +5.0 V 10 % MIN. 125 250 ASCK clock low-level width tWASKL VDD = +5.0 V 10 % 52.5 85 ASCK clock high-level width tWASKH VDD = +5.0 V 10 % 52.5 85 MAX. Unit ns ns ns ns ns ns
69
PD784035(A), 784036(A)
CLOCK OUTPUT OPERATION
Parameter CLKOUT cycle time CLKOUT low-level width Symbol tCYCL tCLL VDD = +5.0 V 10 % Conditions MIN. nT 0.5tCYCL - 10 0.5tCYCL - 20 CLKOUT high-level width tCLH VDD = +5.0 V 10 % 0.5tCYCL - 10 0.5tCYCL - 20 CLKOUT rise time tCLR VDD = +5.0 V 10 % 10 20 CLKOUT fall time tCLF VDD = +5.0 V 10 % 10 20 MAX. Unit ns ns ns ns ns ns ns ns ns
Remarks n: Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16) T: tCYK (system clock cycle time) OTHER OPERATIONS
Parameter NMI low-level width NMI high-level width INTP0 low-level width INTP0 high-level width Low-level width for INTP1INTP3 and CI High-level width for INTP1INTP3 and CI Low-level width for INTP4 and INTP5 Symbol tWNIL tWNIH tWIT0L tWIT0H tWIT1L Conditions MIN. 10 10 4tCYSMP 4tCYSMP 4tCYCPU MAX. Unit
s s
ns ns ns
tWIT1H
4tCYCPU
ns
tWIT2L
10
s s s s
High-level width for INTP4 and tWIT2H INTP5 RESET low-level width RESET high-level width tWRSL tWRSH
10
10 10
Remarks tCYSMP: Sampling clock set by software tCYCPU: CPU operation clock set by software in the CPU
70
PD784035(A), 784036(A)
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total errorNote Linearity calibrationNote Quantization error Conversion time tCONV FR = 1 FR = 0 Sampling time tSAMP FR = 1 FR = 0 Analog input voltage Analog input impedance AVREF1 current AVDD supply current VIAN RAN AIREF1 AIDD1 AIDD2 fXX = 32 MHz, CS = 1 STOP mode, CS = 0 120 180 24 36 -0.3 1 000 0.5 2.0 1.0 1.5 5.0 20 AVREF1 + 0.3 Symbol Conditions MIN. 8 1.0 0.8 1/2 TYP. MAX. Unit bit % % LSB tCYK tCYK tCYK tCYK V M mA mA
A
Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value. Remark tCYK: System clock cycle time
71
PD784035(A), 784036(A)
D/A CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error Load conditions: VDD = AVDD = AVREF2 4 M, 30 pF = +2.7 to 5.5 V AVREF3 = 0 V VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD Load conditions: VDD = AVDD = AVREF2 2 M, 30 pF = +2.7 to 5.5 V AVREF3 = 0 V VDD = AVDD = +2.7 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD Settling time Output resistance Analog reference voltage RO AVREF2 AVREF3 Resistance of AVREF2 and AVREF3 Reference power supply input current RAIREF DACS0, 1 = 55 H Load conditions: 2 M, 30 pF DACS0, 1 = 55 H 0.75VDD 0 4 8 10 VDD 0.25VDD Symbol Conditions MIN. 8 0.6 TYP. MAX. Unit bit %
0.8
%
0.8
%
1.0
%
10
s
k V V k
AIREF2 AIREF3
0 -5
5 0
mA mA
72
PD784035(A), 784036(A)
DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR STOP mode VDDDR = +2.7 to 5.5 V VDDDR = +2.5 V VDD rise time VDD fall time VDD hold time (to STOP mode setting) STOP clear signal input time Oscillation settling time tRVD tFVD tHVD 200 200 0 Conditions MIN. 2.5 10 2 TYP. MAX. 5.5 50 10 Unit V
A A s s
ms
tDREL tWAIT Crystal Ceramic resonator
0 30 5 0 0.9VDDDR 0.1VDDDR VDDDR
ms ms ms V V
Input low voltage Input high voltage
VIL VIH
Specific pinsNote
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins AC TIMING TEST POINTS
VDD - 1 V 0.8VDD or 2.2 V Test points 0.45 V 0.8 V 0.8 V 0.8VDD or 2.2 V
73
PD784035(A), 784036(A)
TIMING WAVEFORM (1) Read operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTID tDRST
tDAID AD0-AD7 tDSTR tDAR RD tWRL tFRA tDRID
tHRA
tHRID tDRA
(2) Write operation
tWSTH ASTB tSAST tHSTLA A8-A19 tDSTOD tDWST
tHWA AD0-AD7 tDSTW tDAW WR tWWL tDWOD tSODW tHWOD
74
PD784035(A), 784036(A)
HOLD TIMING
ADTB, A8-A19, AD0-AD7, RD, WR tFHQC HLDRQ tDHQHHAH HLDAK tDHQLHAL tDCFHA tDHAC
EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT RD tDRWTL WAIT tHRWT tDRWTH tDWTR tDWTID
(2) Write operation
ASTB tDSTWTH tHSTWTH
tDSTWT A8-A19
AD0-AD7 tDAWT WR tDWWTL WAIT tHWWT tDWWTH tDWTW
75
PD784035(A), 784036(A)
REFRESH TIMING WAVEFORM (1) Random read/write cycle
tRC ASTB
WR tRC RD tRC tRC tRC
(2) When refresh memory is accessed for a read and write at the same time
ASTB
RD, WR tDSTRFQ tDRFQST tWRFQH
REFRQ tWRFQL
(3) Refresh after a read
ASTB tDRFQST RD tDRRFQ REFRQ tWRFQL
(4) Refresh after a write
ASTB tDRFQST WR tDWRFQ REFRQ tWRFQL
76
PD784035(A), 784036(A)
SERIAL OPERATION (1) CSI
tWSKL0 SCK tCYSK0 SI tDSBSK1 SO tHSBSK1 tSSSK0 tHSSK0 Input data tWSKH0
Output data
(2) IOE1, IOE2
tWSKL1 SCK tCYSK1 SI tDSOSK SO tHSOSK tSSSK1 tHSSK1 tWSKH1
Input data
Output data
(3) UART, UART2
tWASKH tWASKL
ASCK, ASCK2 tCYASK
77
PD784035(A), 784036(A)
CLOCK OUTPUT TIMING
tCLH tCLL
CLKOUT tCLR tCYCL tCLF
INTERRUPT REQUEST INPUT TIMING
tWNIH
tWNIL
NMI
tWIT0H
tWIT0L
INTP0
tWIT1H
tWIT1L
CI, INTP1-INTP3
tWIT2H
tWIT2L
INTP4, INTP5
RESET INPUT TIMING
tWRSH tWRSL
RESET
78
PD784035(A), 784036(A)
EXTERNAL CLOCK TIMING
tWXH tWXL
X1 tXR tCYX tXF
DATA RETENTION CHARACTERISTICS
STOP mode setting
VDD tHVD tFVD
VDDDR tRVD tDREL tWAIT
RESET
NMI (Clearing by falling edge)
NMI (Clearing by rising edge)
79
PD784035(A), 784036(A)
14. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
CD
S Q R
80 1
21 20
F G H P I
M
J K M N L
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 +0.004 0.006 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. S80GC-65-3B9-5
Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product.
80
PD784035(A), 784036(A)
15. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the PD784035(A) and PD784036(A). For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 15-1. Soldering Conditions for Surface-Mount Devices
PD784035GC(A)-xxx-3B9: 80-pin plastic QFP (14 x 14 mm) PD784036GC(A)-xxx-3B9: 80-pin plastic QFP (14 x 14 mm)
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (210 C or more) Maximum allowable number of reflow processes: 3 Peak package's surface temperature: 215 C Reflow time: 40 seconds or less (200 C or more) Maximum allowable number of reflow processes: 3 Symbol IR35-00-3
VPS
VP15-00-3
Wave soldering
Solder temperature: 260 C or less WS60-00-1 Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature : 120 C max. (measured on the package surface) Terminal temperature: 300 C or less Heat time: 3 seconds or less (for one side of a device) -
Partial heating method
Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections).
81
PD784035(A), 784036(A)
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the PD784036(A). See also (5). (1) Language processing software
RA78K4 CC78K4 DF784038 CC78K4-L Assembler package for all 78K/IV series models C compiler package for all 78K/IV series models Device file for PD784038 sub-series models C compiler library source file for all 78K/IV series models
(2) PROM write tools
PG-1500 PA-78P4026GC PG-1500 controller PROM programmer Programmer adaptor, connects to PG-1500 Control program for PG-1500
(3) Debugging tools * When using the in-circuit emulator IE-78K4-NS
IE-78K4-NSNote IE-70000-MC-PS-B IE-70000-98-IF-CNote IE-70000-CD-IFNote IE-70000-PC-IF-CNote IE-784038-NS-EM1Note NP-80GC EV-9200GC-80 ID78K4-NSNote SM78K4-NS DF784038 In-circuit emulator for all 78K/IV series models Power supply unit for IE-78K4-NS Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine PC card and interface cable when a PC-9800 series notebook is used as the host machine Interface adapter when the IBM PC/ATTM or compatible is used as the host machine Emulation board for evaluating PD784038 sub-series models Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket for mounting on target system board made for 80-pin plastic QFP (GC-3B9 type) Integrated debugger for IE-78K4-NS System simulator for all 78K/IV series models Device file for PD784038 sub-series models
Note Under development
82
PD784035(A), 784036(A)
* When using the in-circuit emulator IE-784000-R
IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-CNote IE-70000-98N-IF-B IE-70000-PC-IF-B IE-70000-PC-IF-CNote IE-78000-R-SV3 IE-784038-NS-EM1Note IE-784038-R-EM1Note IE-78400-R-EM IE-78K4-R-EX2Note In-circuit emulator for all 78K/IV series models Interface adapter when the PC-9800 series computer (other than a notebook) is used as the host machine Interface adapter and cable when a PC-9800 series notebook is used as the host machine Interface adapter when the IBM PC/AT or compatible is used as the host machine Interface adapter and cable when the EWS is used as the host machine Emulation board for evaluating PD784038 sub-series models Emulation board for all 78K/IV series models Conversion board for 80 pins to use the IE-784038-NS-EM1 on the IE-784000-R. The board is not needed when the conventional product IE-784038-R-EM1 is used. Emulation probe for 80-pin plastic QFP (GC-3B9 type) Socket for mounting on target system board made for 80-pin plastic QFP (GC-3B9 type) Integrated debugger for IE-784000-R System simulator for all 78K/IV series models Device file for PD784038 sub-series models
EP-78230GC-R EV-9200GC-80 ID78K4 SM78K4 DF784038
Note Under development (4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV series models OS for 78K/IV series models
83
PD784035(A), 784036(A)
(5) Notes when using development tools * The ID78K-NS, ID78K4, and SM78K4 can be used in combination with the DF784038. * The CC78K and RX78K/IV can be used in combination with the RA78K4 and DF784038. * The NP-80GC is a product from Naito Densei Machida Seisakusho Co., Ltd. (044-822-3813). Consult the NEC sales representative for purchasing. * The host machines and operating systems corresponding to each software are shown below.
Host machine [OS]
PC PC-9800 Series [WindowsTM]
EWS HP9000 Series 700TM [HP-UXTM]
IBM PC/AT and compatibles [Windows] SPARCstationTM [SunOSTM] NEWSTM (RISC) [NEWS-OSTM] Software RA78K4 CC78K4 PG-1500 controller ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
Note Note Note Note Note
-
-
Note Software under MS-DOS
84
PD784035(A), 784036(A)
APPENDIX B RELATED DOCUMENTS
Documents Related to Devices
Document No. Document name Japanese English This manual Under creation To be created U11316E U10905E -
PD784035(A), 784036(A) Data Sheet PD784031(A) Data Sheet PD78P4038(A) Data Sheet PD784038, 784038Y Sub-Series User's Manual, Hardware PD784038 Sub-Series Special Function Registers
78K/IV Series User's Manual, Instruction 78K/IV Series Instruction Summary Sheet 78K/IV Series Instruction Set 78K/IV Series Application Note, Software Basic
U13010J U13009J To be created U11316J U11090J U10905J U10594J U10595J U10095J
Documents Related to Development Tools (User's Manual)
Document No. Document name Japanese RA78K4 Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K4 C Compiler Operation Language CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOSTM) Base U11334J U11162J U11743J U11572J U11571J U12322J U11940J EEU-704 EEU-5008 Under creation U12903J To be created U11383J EEU-985 Reference External Parts User Open Interface Specifications Reference Reference Reference U10093J U10092J English U11334E U11162E U11743E U11572E U11571E U12322E U11940E EEU-1291 U10540E To be created EEU-1534 To be created U11383E EEU-1515 U10093E U10092E
PG-1500 Controller IBM PC Series (PC DOSTM) Base IE-78K4-NS IE-784000-R IE-784038-NS-EM1 IE-784038-R-EM1 EP-78230 SM78K4 System Simulator Windows Base SM78K Series System Simulator
ID78K4 Integrated Debugger ID78K4 Integrated Debugger Windows Base ID78K4 Integrated Debugger HP-UX, SunOS, NEW-OS Base
U12796J U10440J U11960J
U12796E U10440E U11960E
Caution The above documents may be revised without notice. Use the latest versions when you design application systems.
85
PD784035(A), 784036(A)
Documents Related to Software to Be Incorporated into the Product (User's Manual)
Document No. Document name Japanese 78K/IV Series Real-Time OS Basic Installation Debugger OS for 78K/IV Series MX78K4 Basic U10603J U10604J U10364J U11779J English U10603E U10604E -
Other Documents
Document No. Document name Japanese IC PACKAGE MANUAL Semiconductor Mount Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide for Products Related to Micro-Computer: Other Companies C10535J C11531J C10983J U11892J C12769J C11416J C10943X C10535E C11531E C10983E E11892E English
Caution The above documents may be revised without notice. Use the latest versions when you design application systems.
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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IEBus is a trademark of NEC Corporation. MS-DOS and Windows are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
J97. 8
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Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
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